Design of Low Power Test Pattern Generator using Low Transition LFSR for high Fault Coverage Analysis
نویسندگان
چکیده
منابع مشابه
Vlsi Design of Low Transition Low Power Test Pattern Generator Using Fault Coverage Circuits
Now a day’s highly integrated multi layer board with IC’s is virtually impossible to be accessed physically for testing. The major problem detected during testing a circuit includes test generation and gate to I/O pin problems. In design of any circuit, consuming low power and less hardware utilization is an important design parameter. Therefore reliable testing methods are introduced which red...
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Abstact A new design approach is proposed for a fault coverage circuit. In this design a linear feedback shift register which is called as LT_LFSR (Low Transition Linear Feedback Shift Register) is used. Using LT_LFSR reduces the power consumption by reducing the number of transitions during test mode. Power reduction is done by implementing two new test pattern generation methods in LFSR. In b...
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A Low Transition LFSR(LT-LFSR) designed by modifying Linear Feedback Shift Register is proposed to produce low power test vectors which are given to Circuit under Test (CUT) to reduce the power consumption by CUT. This technique of generating low power test patterns is performed by increasing the co-relativity between the consecutive vectors by reducing the number of bit flips between successiv...
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This paper describes a low-power test generation procedure, which targets the switching activity during the fast functional clock cycles of broadside tests. The procedure is based on merging of test cubes that it extracts from functional broadside tests. The use of test cube merging supports test compaction and it can be used for accommodating the constraints of test data compression. The use o...
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ژورنال
عنوان ژورنال: International Journal of Information Engineering and Electronic Business
سال: 2013
ISSN: 2074-9023,2074-9031
DOI: 10.5815/ijieeb.2013.02.03